SN74LS112AN
Flip-Flop, 74LS112, JK, 15 ns, 30 MHz, 8 mA, DIP
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| Quantity | Price (ex VAT) |
|---|---|
| 1+ | Kč24.754 |
| 10+ | Kč17.832 |
| 50+ | Kč17.807 |
| 100+ | Kč17.757 |
| 250+ | Kč17.732 |
| 500+ | Kč17.706 |
| 1000+ | Kč17.656 |
| 2500+ | Kč17.631 |
Product Information
Product Overview
The SN74LS112AN is a dual J-K Negative-Edge-Triggered Flip-Flop with clear and preset. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. This versatile flip-flop can perform as toggle flip-flop by tying J and K high. The SN74S112A is characterized for operation from 0 to 70°C.
- Fully buffered to offer maximum isolation from external disturbance
- Quality and reliability
- Green product and no Sb/Br
Applications
Communications & Networking
Technical Specifications
74LS112
15ns
8mA
DIP
Negative Edge
4.75V
74LS
0°C
-
-
JK
30MHz
DIP
16Pins
Complementary
5.25V
74112
70°C
-
No SVHC (27-Jun-2018)
Legislation and Environmental
Country in which last significant manufacturing process was carried outCountry of Origin:Malaysia
Country in which last significant manufacturing process was carried out
RoHS
RoHS
Product Compliance Certificate