SY87700ALHG

The SY87700ALHG is a complete Clock Recovery and Data Retiming Integrated Circuit for data rate from 32 up to 208Mbps NRZ. The device is ideally suited for SONET/SDH/ATM applications and other high-speed data transmission systems. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO centre frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference. The SY87700AL also includes a link fault detection circuit.

• SONET/SDH/ATM compatible
• Two on-chip PLLs - One for clock generation and another for clock recovery
• Differential PECL high-speed serial I/O
• Line receiver input - No external buffering needed
• Link fault indication
• 100k ECL compatible I/O
• Lower power - Fully compatible with Micrel's SY87700V, but with 30% less power